EDP INTERFACE AND CONTROL METHOD OF TRANSMISSION RATE OF EDP INTERFACE

摘要

The present invention discloses an eDP interface, including: a determination module, a clock signal generating module, a clock signal adjusting module, a first eDP data processing chip and a second eDP data processing chip. When the determination module determines that a target transmission rate is not equal to a protocol rate, the clock signal generating module generates a first clock signal and a second clock signal. The clock signal adjusting module adjusts the frequency of the second clock signal. The first and second eDP data processing chips process data according to the first and second clock signals, respectively.

主权项

1. An eDP interface, comprising:
a determination module, which is configured to determine whether a target transmission rate in a lane is equal to a protocol rate set in an eDP protocol; a clock signal generating module, which is configured to generate a first clock signal and a second clock signal when the target transmission rate is not equal to the protocol rate, and send the first clock signal to a first eDP data processing chip and send the second clock signal to a clock signal adjusting module; the clock signal adjusting module, which is configured to adjust a frequency of the second clock signal and send the adjusted second clock signal to a second eDP data processing chip; the first eDP data processing chip, which is configured to process data according to the first clock signal and send the processed data to the lane for transmission; and the second eDP data processing chip, which is configured to process data according to the adjusted second clock signal and send the processed data to the lane for transmission.