| 摘要 |
<p>A vertical transistor includes a drain electrode (106) disposed on a first region of a substrate (102), a drift layer (108) disposed on a second region of the substrate spaced apart from the first region, and P-type gallium nitride current barrier layers (110) disposed on the drift layer and comprising a current aperture (109) disposed between current barrier layers. A channel layer (112) is disposed on the drift layer and the current barrier layers. A semiconductor layer (114) is disposed on the channel layer and configured to induce formation of a two-dimension electron gas layer (113) adjacent to a top surface thereof. Metal contact plugs (124) are disposed in the channel layer and contact the current barrier layers. A source electrode (116) is disposed on the contact plugs and the channel layer. A gate insulation layer (118) and a gate electrode (120) are sequentially disposed on a top surface of the semiconductor layer opposite to the channel layer.</p> |
