| 摘要 |
A frequency-locked loop for generating a clock signal comprises a controllable oscillator (101, fig.1), a frequency divider 202, (102, fig.1) and a frequency detector 205, (104, fig.1) arranged to control the oscillator. The divider 202 comprises a first counter 203 clocked by the oscillator, and a second counter 204 clocked by the first counter. The first counter may be a twisted ring counter (303, fig.3) and the second counter may be a linear feedback shift register (LFSR) (304, fig.3). Alternatively, the second counter may be a ripple counter. These types of counter are preferred over a synchronous counter as they require less logic between flip-flops and thus consume less power. It is disclosed that the state of the counter 203/204 may be held in state register 401/402. The state of the counter logic may be measured at both bounds of a first time interval and the frequency of the oscillator may be estimated from a determined number of elapsed states of the counter logic in the first time interval. The frequency detector may implement a trellis network to detect and correct errors in the determined oscillator frequency. |
