发明名称 |
TIME-TO-DIGITAL CONVERTER, ALL DIGITAL PHASE LOCKED LOOP CIRCUIT, AND METHOD |
摘要 |
The present invention discloses a time-to-digital converter. The time-to-digital converter includes: a phase interpolation circuit and a time-to-digital conversion circuit. The phase interpolation circuit is configured to receive a first reference clock signal and a second reference clock signal; perform phase interpolation on the first reference clock signal and the second reference clock signal to generate a third reference clock signal; and output the third reference clock signal to the time-to-digital conversion circuit. The time-to-digital conversion circuit is configured to receive the third reference clock signal and a fourth clock signal, where a phase difference between the third reference clock signal and the fourth clock signal is less than a phase difference between the first reference clock signal and the fourth clock signal; measure the phase difference between the third reference clock signal and the fourth clock signal; and convert the measured phase difference into a digital signal for outputting. |
申请公布号 |
EP2940872(A1) |
申请公布日期 |
2015.11.04 |
申请号 |
EP20150166061 |
申请日期 |
2015.04.30 |
申请人 |
HUAWEI TECHNOLOGIES CO., LTD. |
发明人 |
ZHOU, SHENGHUA;LI, XIAOYU |
分类号 |
H03L7/085;G04F10/00 |
主分类号 |
H03L7/085 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|