Feedback amplifier

摘要

Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a burst packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a burst packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.

主权项

1. A feedback amplifier comprising:
an amplification circuit unit amplifying a burst packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a burst packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage; wherein the feedback circuit unit comprises: a feedback transistor where a base receives the bias voltage, a collector is connected to the input terminal, and an emitter is connected to the output terminal; and a feedback resistance unit connected in parallel to the feedback transistor; wherein the feedback resistance unit comprises: a fixed resistor connected between the input terminal and the output terminal; and at least one feedback resistor connected in parallel to the fixed resistor; and wherein the packet signal detection unit comprises: a detection diode detecting a peak value of a burst packet signal of the output node: a detection NAND gate receiving the detected peak value and a detection reference voltage and outputting a NAND operation result through a NAND operation; and a detection transistor connected in parallel to the fixed resistor and performs one of an on operation and an off operation according to the NAND operation result to control the fixed resistance value.