发明名称 Power supply device
摘要 A power supply device has a first delay circuit which delays a first clock signal and outputs a second clock signal, a pulse signal generating circuit which generates a first pulse signal, a first transistor which connects an output node to a power supply potential node according to the first pulse signal, a second transistor which connects the output node to a reference potential node according to the first pulse signal, an integration circuit which integrates and outputs a signal of the output node, and a comparator which compares an output signal of the integration circuit and the reference signal, wherein the pulse signal generating circuit generates the first pulse signal in synchronization with the first clock signal, the second clock signal and the output signal of the comparator, and the frequency of the first pulse signal is constant irrespective of voltage of the output node.
申请公布号 US9178425(B2) 申请公布日期 2015.11.03
申请号 US201414574660 申请日期 2014.12.18
申请人 FUJITSU LIMITED 发明人 Nakao Hiroshi
分类号 G05F1/00;H02M3/158 主分类号 G05F1/00
代理机构 Fujitsu Patent Center 代理人 Fujitsu Patent Center
主权项 1. A power supply device, comprising: a first delay circuit which delays a first clock signal and outputs a second clock signal; a pulse signal generating circuit which generates a first pulse signal in synchronization with the first clock signal; a first transistor which connects an output node to a power supply potential node according to the first pulse signal; a second transistor which connects the output node to a reference potential node according to the first pulse signal; an integration circuit which integrates and outputs a signal of the output node; and a comparator which compares an output signal of the integration circuit and the reference signal, wherein the first transistor and the second transistor perform on and off operations which are reverse to each other, the pulse signal generating circuit sets the first pulse signal to first level in synchronization with the first clock signal, sets the first pulse signal to second level in synchronization with the second clock signal, and sets the first pulse signal to the second level in synchronization with an output signal of the comparator, and the frequency of the first pulse signal is constant irrespective of voltage of the output node.
地址 Kawasaki JP