Jittering frequency control circuit and method for a switching mode power supply

摘要

A jittering frequency control circuit and method for a switching mode power supply enlarge the uttering frequency range of the switching frequency of the switching mode power supply when the switching mode power supplier enters a frequency reduction mode, to improve the electro-magnetic interference of the switching mode power supply operating with the frequency reduction mode.

主权项

1. A jittering frequency control circuit for a switching mode power supply, comprising:
an oscillator configured to operably provide a clock having a jittering frequency to determine a switching frequency of the switching mode power supply; and a jittering frequency modulator connected to the oscillator, operative to generate a jittering frequency adjust signal according to an output feedback signal of the switching mode power supply and a reference signal provided by the oscillator and supply the jittering frequency adjust signal to the oscillator to control a jittering frequency range of the switching frequency; wherein the jittering frequency modulator comprises:
a capacitor configured to operably provide a voltage as the jittering frequency adjust signal;a current mirror configured to operably generate a charge current and a discharge current according to the reference signal;a first switch connected between the capacitor and the current mirror, responsive to a first signal to switch the charge current to charge the capacitor;a second switch connected between the capacitor and the current mirror, responsive to a second signal to switch the discharge current to discharge the capacitor;a first comparator connected to the capacitor, having a negative input terminal to receive the jittering frequency adjust signal;a second comparator connected to the capacitor, having a positive input terminal to receive the jittering frequency adjust signal;a third comparator configured to operably compare the output feedback signal with a threshold to generate a comparison signal;a first selector connected to the first comparator and the third comparator, operative to select one of a normal upper limit and a frequency reduction upper limit according to the comparison signal to supply to a positive input terminal of the first comparator;a second selector connected to the second comparator and the third comparator, operative to select one of a normal lower limit and a frequency reduction lower limit according to the comparison signal to supply to a negative input terminal of the second comparator; anda flip-flop connected to the first comparator and the second comparator operative to determine the first signal and the second signal according to an output of the first comparator and an output of the second comparator.