主权项 |
1. A method of forming an integrated circuit, comprising the steps:
providing a substrate comprising semiconductor material at a top surface of said substrate; forming a gate of an analog metal oxide semiconductor (MOS) transistor over said substrate, said analog MOS transistor having a first source/drain gate edge at said top surface of said substrate directly under a first lateral surface of said gate and having a second source/drain gate edge at said top surface of said substrate directly under a second lateral surface of said gate, so that said first source/drain gate edge and said second source/drain gate edge are on opposite sides of said gate; forming an implant mask over said substrate so as to expose at least a portion of said gate and expose a portion of said substrate adjacent to said gate, so that said implant mask is separated from said first source/drain gate edge, and is separated from said second source/drain gate edge, by substantially equal lateral spaces; and forming drain extensions in said substrate adjacent to, and partially underlapping, said gate at said first source/drain gate edge and said second source/drain gate edge by implanting dopants in four sub-implants, wherein:
a first sub-implant of said four sub-implants is at a tilt angle of at least 15 degrees, referenced to a perpendicular line to said top surface of said substrate, and at a first twist angle having a magnitude of 5 degrees to 40 degrees referenced to a horizontal normal line which lies in said top surface and is perpendicular to said first source/drain gate edge, wherein said first sub-implant clears said implant mask to implant a portion of said dopants into said substrate at said first source/drain gate edge, said first sub-implant being blocked from said second source/drain gate edge by said gate;a second sub-implant of said four sub-implants is at said tilt angle of at least 15 degrees and at a second twist angle referenced to said horizontal normal line opposite from said first twist angle, wherein said second sub-implant clears said implant mask to implant a portion of said dopants into said substrate at said first source/drain gate edge, said second sub-implant being blocked from said second source/drain gate edge by said gate;a third sub-implant of said four sub-implants is at said tilt angle of at least 15 degrees and opposite from said first sub-implant, wherein said third sub-implant clears said implant mask to implant a portion of said dopants into said substrate at said second source/drain gate edge, said third sub-implant being blocked from said first source/drain gate edge by said gate;a fourth sub-implant of said four sub-implants is at said tilt angle of at least 15 degrees and opposite from said second sub-implant, wherein said fourth sub-implant clears said implant mask to implant a portion of said dopants into said substrate at said second source/drain gate edge, said fourth sub-implant being blocked from said first source/drain gate edge by said gate; andsaid drain extensions are free of halo implanted regions having dopants of an opposite conductivity type from said dopants of said four sub-implants. |