Sub-threshold FPGA and related circuits and methods thereof

摘要

A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.

主权项

1. A field programmable gate array (FPGA), comprising:
a circuit configured to operate in a sub-threshold voltage range, wherein said circuit has a VDD level that is less than a threshold voltage of transistors in said circuit, wherein said circuit employs a low-swing signaling scheme, and wherein said low-swing signaling scheme is a signaling with a voltage swing that is less than said VDD level.