| 主权项 |
1. A system for protecting a circuit from an electrostatic discharge (ESD) voltage, the system comprising:
an input terminal for receiving an input signal; an ESD protection circuit configured to receive the input signal from the input terminal, the ESD protection circuit including one or more vertical nanowire field effect transistors (FETs), wherein each of the one or more vertical nanowire FETs includes:
a well of a first conductivity type that is formed in a semiconductor substrate,a nanowire having i) a source region at a first end of the nanowire, and ii) a drain region at a second end of the nanowire that is opposite the first end, the source region further including a portion formed in the well, wherein the source region and the drain region are of a second conductivity type such that a PN junction is formed between the well and the portion of the source region formed in the well, anda gate region surrounding a portion of the nanowire, wherein the gate region is separated from the drain region by a first distance, the separation of the gate region and the drain region providing a resistance in series between the drain region and the source region; and an output terminal configured to receive the input signal from the ESD protection circuit, wherein an ESD-induced voltage in the input signal is attenuated by the resistance and the PN junction. |
