Innovative approach of 4F²driver formation for high-density RRAM and MRAM

摘要

Some embodiments of the present disclosure relate to a vertical MOSFET selection transistor that is configured to suppress leakage voltage in the memory cell without limiting the size of the memory cell. The memory selection transistor has a semiconductor body with first and second trenches that define a raised semiconductor structure having a source region, a channel region, and a drain region. A gate structure has a first gate electrode in the first trench, which extends vertically along a first side of the raised semiconductor structure, and a second gate electrode in the second trench, which extends vertically along an opposite, second side of the raised semiconductor structure. The first and second gate electrodes collectively control the flow of current between the source and drain region in the raised semiconductor structure. An electrical contact couples the drain region to a data storage element configured to store data.

主权项

1. A memory cell, comprising:
a semiconductor body having a first trench and a second trench that form a raised semiconductor structure having a source region and a drain region vertically separated by a channel region, wherein the first trench and the second trench extend within the semiconductor body to a depth that is greater than that of the channel region; a first gate electrode comprised within the first trench and vertically extending along a first sidewall of the first trench; a second gate electrode comprised within the second trench and vertically extending along a second sidewall of the second trench; a first metal contact comprised within a dielectric material disposed over the semiconductor body and configured to couple the drain region to a data storage element configured to store data; an isolation dielectric material disposed within the first and second trenches at positions that vertically abut to surfaces of the first and second gate electrodes and that laterally abut sidewalls of the first and second gate electrodes; and wherein the first trench and the second trench comprise sidewalls that are tapered from a top surface of the raised semiconductor structure to bottom surfaces of the first and second trenches.