Timing closure using transistor sizing in standard cells

摘要

An approach is provided in which a design tool executes static timing analysis of an integrated circuit design using a first set of timing values corresponding to a first set of layout properties of a transistor included in a standard cell utilized by the integrated circuit design. When the design tool determines that the static timing analysis generates a timing violation within a violation budget, the design tool selects a second set of timing values of the standard cell corresponding to a second set of layout properties of the transistor. The design tool determines that re-execution of the static timing analysis using the second set of timing values resolves the timing violation and, in turn, generates mask layer data that includes the second set of layout properties.

主权项

1. A system comprising:
one or more processors; a memory accessible by the one or more processors; a design tool module executed by at least one of the one or more processors and configured to:
create a standard cell that includes a first set of layout properties and a second set of layout properties of a transistor included in a timing path in the standard cell, wherein the second set of layout properties is stored into a resize layer entry of annotated cell layout data associated with the standard cell;execute a first static timing analysis of an integrated circuit design using a first set of timing values, the first set of timing values corresponding to the first set of layout properties of the transistor included in the standard cell utilized by the integrated circuit design;execute a second static timing analysis of the integrated circuit design using a second set of timing values in response to a detection that the first static timing analysis generates a timing violation, the second set of timing values corresponding to the second set of layout properties of the transistor included in the standard cell; andgenerate mask layer data that includes the second set of layout properties in response to a determination that the second static timing analysis resolves the timing violation, wherein the mask layer data is configured to generate a plurality of masks for construction of an integrated circuit corresponding to the integrated circuit design.