发明名称 Multi-level encoded data transfer
摘要 Multi-level encoded data transfer is disclosed. 2n bits may be encoded in a data signal each half clock cycle. For example, four bits may be transferred each clock cycle. Prior to data transfer, each data line may have two bits ready to be encoded. The two bits may be encoded to one of four different data states. The clock may be divided into four intervals for each half clock cycle, with each interval corresponding to one of the four data states. The two bits may be encoded into the data signal based on the interval that corresponds to the data state. As one example, the data signal could transition during the interval that corresponds to the data state for the two bits. This encoding may be repeated for two other bits for the other half of the clock cycle. Thus, QDR or some other data rate may be achieved.
申请公布号 US9176920(B2) 申请公布日期 2015.11.03
申请号 US201213659713 申请日期 2012.10.24
申请人 SanDisk Technologies Inc. 发明人 Liu Michael Ming-Chang;Jin Darmin
分类号 G06F13/42;G06F1/08;G06F1/12 主分类号 G06F13/42
代理机构 Vierra Magen Marcus LLP 代理人 Vierra Magen Marcus LLP
主权项 1. A method comprising: accessing, by a transmitter circuit, a plurality of groups of data bits, each group of data bits having one of 2n data states, wherein each group includes at least two data bits; associating, by the transmitter circuit, each group of data bits with one section of a clock, including associating at least four data bits per each cycle of the clock; determining, by the transmitter circuit, 2n successive time intervals per section of the clock, there being a one-to-one association between the 2n data states and the 2n successive time intervals; associating, by the transmitter circuit, each group of data bits with one of the 2n successive time intervals based on the one-to-one association between the 2n data states and the 2n successive time intervals; and generating, by the transmitter circuit, a data signal based on the section of the clock associated with each group of data bits and the time interval associated with each group of data bits, wherein the generating includes encoding each group of data bits in a portion of the data signal that corresponds to one section of the clock, encoding at least four data bits per each cycle of the clock, encoding all but one of the 2n data states as a transition in the data signal, wherein the transition for encoding a particular data state occurs during the time interval associated with the particular data state, and encoding one of the 2n data states as a constant level in the data signal for a duration of one section of the clock.
地址 Plano TX US