发明名称 Memory access during memory calibration
摘要 A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.
申请公布号 US9176903(B2) 申请公布日期 2015.11.03
申请号 US201113883542 申请日期 2011.11.07
申请人 Rambus Inc. 发明人 Shaeffer Ian;Ware Frederick A.
分类号 G06F13/16 主分类号 G06F13/16
代理机构 Fenwick & West LLP 代理人 Fenwick & West LLP
主权项 1. A method of controlling first and second ranks of memory devices, coupled to a memory controller, via data buses that include at least a first data bus and a second data bus both of which are coupled to a first memory device in the first memory rank and a second memory device in the second memory rank, the method comprising: performing a calibration operation that pertains to transmission of data between the first memory device and the memory controller via the first data bus; and while performing the calibration operation, transferring data, via the second data bus, between the second memory device and the memory controller.
地址 Sunnyvale CA US