主权项 |
1. A low-pin-count non-volatile memory (NVM) integrated in an integrated circuit, the NVM comprising:
a plurality of NVM cells; at least one of the NVM cells including at least:
an NVM element coupled to a first supply voltage line; anda selector coupled to the NVM element and a second supply voltage line having a select signal; a first signal input for receiving a first signal; and a second signal input for receiving a second signal, wherein a transaction starts based on a voltage level of the first signal during a transition of the second signal, wherein the transaction includes at least one mode cycle and a plurality of data cycles to specify operation modes and programming, erasing, or reading the NVM cells, respectively, once the transaction starts, and wherein the NVM cells are selected sequentially for program, erase, or read when the voltage of the first signal is coupled to the first or second supply voltage level during the data cycles.; |