发明名称 LOW-PIN-COUNT NON-VOLATILE MEMORY INTERFACE WITH SOFT PROGRAMMING CAPABILITY
摘要 A low-pin-count non-volatile (NVM) memory with no more than two control signals that can at least program NVM cells, load data to be programmed into output registers, or read the NVM cells. At least one of the NVM cells has at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector is coupled to a second supply voltage line and having a select signal. No more than two control signals can be used to select the at least one NVM cells in the NVM sequentially for programming the data into the at least one NVM cells or loading data into the at least one output registers. Programming into the NVM cells, or loading data into output registers, can be determined by the voltage levels of the first to the second supply voltage lines.
申请公布号 US2015310927(A1) 申请公布日期 2015.10.29
申请号 US201514792479 申请日期 2015.07.06
申请人 Chung Shine C. 发明人 Chung Shine C.
分类号 G11C17/18;G11C17/16;G11C13/00;G11C16/04 主分类号 G11C17/18
代理机构 代理人
主权项 1. A low-pin-count non-volatile memory (NVM) integrated in an integrated circuit, the NVM comprising: a plurality of NVM cells; at least one of the NVM cells including at least: an NVM element coupled to a first supply voltage line; anda selector coupled to the NVM element and a second supply voltage line having a select signal; a first signal input for receiving a first signal; and a second signal input for receiving a second signal, wherein a transaction starts based on a voltage level of the first signal during a transition of the second signal, wherein the transaction includes at least one mode cycle and a plurality of data cycles to specify operation modes and programming, erasing, or reading the NVM cells, respectively, once the transaction starts, and wherein the NVM cells are selected sequentially for program, erase, or read when the voltage of the first signal is coupled to the first or second supply voltage level during the data cycles.;
地址 San Jose CA US