ERROR RECOVERY CIRCUIT FACING CPU ASSEMBLY LINE

摘要

Disclosed is an error recovery circuit facing a CPU assembly line, comprising: on-chip monitoring circuits (1), an error signal statistics module (2), a voltage frequency control module (3), an error recovery control module (4), an in-situ error recovery module (5) and an upper-layer error recovery module (6), wherein each of the on-chip monitoring circuits (1) is integrated at the end of each stage of assembly lines of the previous N−1 stages of assembly lines of a CPU kernel with an N-stage assembly line structure, so as to monitor the time sequence information about each clock period of an operating circuit, wherein N is a positive integer which is greater than or equal to 3 and less than 20. The present invention provides the on-line time sequence monitoring on the CPU kernel with N stages of assembly lines to search for the lowest possible operating voltage of the circuit, and to reduce the margin of the operating voltage reserved for the circuit in the design stage, thereby significantly reducing the power consumption of the circuit and improving the energy efficiency of the circuit.

主权项

1. An error recovery circuit oriented to CPU pipelines, comprising on-chip monitoring circuits, an error signal statistics module, a voltage and frequency control module, an error recovery control module, a local error recovery module, and a global error recovery module, wherein:
the on-chip monitoring circuit is integrated at the terminal of each of the first N−1 pipeline stages of a CPU core in N-stage pipeline architecture, and monitors the time sequence information of each clock cycle in the operating circuit, where, N is a positive integer greater than or equal to 3 but smaller than 20; the on-chip monitoring circuit feeds any error signals detected by it into the error signal statistics module; the error signal statistics module performs statistics on the percentage of the number of error signals in a specific number of clock cycles to the total number of clock cycles, and such percentage is considered as error ratio Rerror; the voltage and frequency control module controls the increase and decrease of the operating voltage and frequency of the system as well as the control accuracy, and the voltage and frequency control module and error signal statistics module feed system state and error ratio Rerror into the error recovery control module respectively; the voltage and frequency control module regulates the operating voltage and frequency of the system according to the control signals from the error recovery control module; the error recovery control module has a preset comparative threshold Tthreshold in it, and determines whether to input a local error recovery mode selection signal into the local error recovery module or to input a global error recovery mode selection signal into the global error recovery module, so as to select local error recovery mode or global error recovery mode dynamically according to the result generated in a threshold comparison and selection mechanism, and sends a voltage and frequency control signal to the voltage and frequency control module to instruct system state regulating, so as to realize dynamic switchover between two different error recovery modes.