SCALABLE SERIAL/DE-SERIAL I/O FOR CHIP-TO-CHIP CONNECTION BASED ON MULTI-FREQUENCY QAM SCHEME

摘要

A serializer and de-serializer circuit which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scalable and utilize a multi-frequency quadrature amplitude modulation (QAM) mechanism for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. The serializer has multiple digital-to-analog converters (DACs) whose outputs are directed to QAM mixer inputs, within QAMs at multiple frequencies, whose outputs are summed into a single analog signal for communication over an I/O connection. The de-serializer amplifies the analog signal which is received by QAM mixers at different frequencies, whose outputs are low pass filtered and converted back to parallel digital data bits.

主权项

1. An apparatus for serializing and de-serializing chip-to-chip communications, comprising:
(a) a serializer configured for integration within a first integrated circuit chip, comprising:
(i) multiple digital-to-analog converters (DACs) configured for converting N parallel bits of digital data to M analog signals, wherein N is an integer value which is at least two times larger than M;(ii) one or more mixers at each of multiple frequencies configured for performing analog modulation;(iii) wherein each said mixer receives one of said M analog signals and a modulation carrier; and(iv) an adder configured for summing outputs from each of said multiple mixers at said multiple frequencies into an I/O output; and (b) a de-serializer configured for integration within a second integrated circuit chip, comprising:
(i) an amplifier configured for amplifying said I/O output from said serializer;(ii) one or more mixers at each of multiple frequencies configured for performing analog demodulation;(iii) wherein each said mixer receives said I/O output from said serializer containing said M analog signals, and a modulation carrier;(iv) a low pass filter coupled to an output of each said mixer; and(v) multiple digital-to-analog converters (DACs), each said DAC receiving input from each said low pass filter, and outputting digital data bits; (c) wherein a given number of parallel digital data bits are converted to a serial analog signal, configured for communication over a single I/O line by the serializer to a de-serializer in a second chip which de-serializes the analog information back into the original parallel digital data bits.