ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL)

摘要

An all-digital phase-locked loop (ADPLL) is provided. The ADPLL comprises a first circuit and a second circuit. The first circuit is configured to monitor a first signal and set a voltage of a second signal to a voltage within a first voltage range when a code of fine-tuning is equal to a first specified value. The first circuit is configured to set a voltage of a third signal to a voltage within a second voltage range when the code of fine-tuning is equal to a second specified value. The second circuit is configured to increase a code of coarse-tuning when the voltage of the second signal is within the first voltage range, and decrease the code of coarse-tuning when the voltage of the third signal is within the second voltage range. The ADPLL provides a target frequency despite changes in at least one of process, voltage or temperature.

主权项

1. An all-digital phase-locked loop (ADPLL), comprising:
a first circuit, configured to:
monitor a first signal, the first signal comprising a code of fine-tuning;output a second signal, the second signal having a voltage within a first voltage range when the code of fine-tuning is equal to a first specified value; andoutput a third signal, the third signal having a voltage within a second voltage range when the code of fine-tuning is equal to a second specified value; and a second circuit, configured to:
output a fourth signal, the fourth signal comprising a code of coarse-tuning;increase the code of coarse-tuning when the voltage of the second signal is within the first voltage range; anddecrease of the code of coarse-tuning when the voltage of the third signal is within the second voltage range.