发明名称 |
ABOVE MOTHERBOARD INTERPOSER WITH QUARTER WAVELENGTH ELECTRICAL PATHS |
摘要 |
A multi-layer interposer substrate includes multiple layers of single interposer substrates. Each single interposer substrate has a first array of interposer interconnects, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects, a second array of interposer interconnects, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate, and at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects. The conductive trace has a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects. An array of connections for a peripheral circuit on each single interposer is connected to the at least one conductive trace. |
申请公布号 |
US2015313017(A1) |
申请公布日期 |
2015.10.29 |
申请号 |
US201514790302 |
申请日期 |
2015.07.02 |
申请人 |
MORGAN / WEISS TECHNOLOGIES INC. |
发明人 |
Johnson Morgan;Weiss Frederick G. |
分类号 |
H05K1/11;H05K1/14;H05K1/02 |
主分类号 |
H05K1/11 |
代理机构 |
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代理人 |
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主权项 |
1. A multi-layer interposer substrate, comprising:
multiple layers of single interposer substrates stacked to form the multi-layer interposer substrate, each single interposer substrate, comprising: a first array of interposer interconnects in the single interposer substrate, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects; a second array of interposer interconnects in the single interposer substrate, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate; and at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects, the conductive trace arranged to have a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects; and an array of connections for a peripheral circuit on each single interposer connected to the at least one conductive trace. |
地址 |
Beaverton OR US |