发明名称 EFFICIENT STORAGE ARCHITECTURE FOR LOW-DENSITY PARITY-CHECK DECODING
摘要 A low-density parity-check (LDPC) decoder may comprise a shift register configured to receive LDPC coded data, perform an iteration associated with decoding the LDPC coded data, and provide a result of performing the iteration. The shift register may include a quantity of lanes corresponding to a quantity of data words received by the shift register at a particular clock cycle, a quantity of stages corresponding to a quantity of clock cycles needed to perform the iteration, a quantity of storage elements, associated with storing the data words during the iteration, and a set of check node elements associated with updating the data words during the iteration. The quantity of stages times the quantity of lanes may be greater than the quantity of storage elements by a particular number of storage elements. The particular number of storage elements may be displaced by the set of check node elements.
申请公布号 US2015311918(A1) 申请公布日期 2015.10.29
申请号 US201414319503 申请日期 2014.06.30
申请人 Infinera Corporation 发明人 PRINGLE Scott G.;KARIMI Mehdi;THOMSON Sandy;WU Yuejian
分类号 H03M13/11;H04L1/00 主分类号 H03M13/11
代理机构 代理人
主权项 1. A low-density parity-check (LDPC) decoder, included in a receiver, comprising: a shift register configured to: receive LDPC coded data; perform an iteration associated with decoding the LDPC coded data; and provide a result of performing the iteration associated with decoding the LDPC coded data; where the shift register includes: a quantity of lanes corresponding to a quantity of data words received by the shift register at a particular clock cycle;a quantity of stages corresponding to a quantity of clock cycles needed to perform the iteration associated with decoding the LDPC coded data; anda quantity of storage elements, associated with storing the data words during the iteration, and a set of check node elements associated with updating the data words during the iteration, a value of the quantity of stages times a value of the quantity of lanes being greater than a value of the quantity of storage elements by a value representing a particular number of storage elements, the particular number of storage elements being displaced by the set of check node elements.
地址 Sunnyvale CA US