Ground Fault Detector With Self-Test

摘要

An apparatus includes an interruption circuit in a power delivery path, and a fault detection circuit configured to provide a fault signal to selectively cause the interruption circuit to interrupt power delivery, wherein the fault detection circuit includes a fault detection integrated circuit (IC) and a sensing coil configured to sense a differential current between a phase conductive path and a neutral conductive path in the power delivery path. A processor is configured to selectively control a fault simulation circuit to simulate a fault in the power delivery path, detect a response of the fault detection circuit to the simulated fault, and determine if the response of the fault detection circuit is an expected response. The processor provides an override signal to the interruption circuit to prevent the interruption circuit from receiving a fault signal from the fault detection circuit during, and for a predetermined time after, the simulated fault.

主权项

1. An apparatus, comprising:
an interruption circuit electrically connected in a power delivery path, the power delivery path including a phase conductive path and a neutral conductive path; a fault detection circuit coupled to the interruption circuit and configured to provide a fault signal to selectively cause the interruption circuit to interrupt power delivery in at least one of the phase conductive path and the neutral conductive path, wherein the fault detection circuit includes a sensing coil configured to sense a differential current between the phase conductive path and the neutral conductive path, and further includes a comparator-type fault detection integrated circuit (IC) that compares the differential current to a threshold; a fault simulation circuit; and a processor coupled to the fault simulation circuit and the fault detection circuit, the processor configured to
selectively control the fault simulation circuit to simulate a fault in the power delivery path;detect a response of the fault detection circuit to the simulated fault; anddetermine if the response of the fault detection circuit is an expected response;wherein the processor provides an override signal to the interruption circuit to prevent the interruption circuit from receiving a fault signal from the fault detection circuit during, and for a predetermined time after, the simulated fault.