VERIFICATION OF BANDGAP REFERENCE STARTUP

摘要

A bandgap reference (BGR) startup verification circuit includes a current minor for receiving an output current from a bandgap reference (BGR) circuit and generating output currents therefrom. A first verification sub-circuit is coupled to receive a first output current to generate a detection voltage (Vdet) and includes a voltage comparator receiving Vdet and a voltage output of the BGR circuit (VBG) to provide a first verification output. A second verification sub-circuit including a voltage comparator is coupled to receive a second output current and a second reference current and provide a second verification output. A third verification sub-circuit includes a current comparator coupled to receive a third output current and a third reference current and provide a third verification output. A digital state machine has inputs receiving the first, second and third verification output, and circuitry for processing these outputs to determine whether the BGR circuit has properly started.

主权项

1. A bandgap reference (BGR) startup verification circuit (temp reference numbers: 100), comprising:
a current mirror for receiving an output current from a bandgap reference (BGR) circuit and generating first, second and third output currents therefrom; a first verification sub-circuit coupled to receive said first output current and generate a detection voltage (Vdet), said first verification sub-circuit comprising a voltage comparator coupled to receive said Vdet and a voltage output of said BGR circuit (VBG) and provide a first verification output; a second verification sub-circuit comprising a voltage comparator coupled to receive said second output current and a second reference current and provide a second verification output; a third verification sub-circuit comprising a current comparator coupled to receive said third output current and a third reference current and provide a third verification output, and a digital logic state machine (digital state machine) having respective inputs coupled for receiving said first verification output, receiving said second verification output, and receiving said third verification output, and circuitry for processing said first verification output, said second verification output and said third verification output to determine whether said BGR circuit has properly started.