| 摘要 |
A three-dimensional semiconductor device, comprising a plurality of storage units and a plurality of selection transistors, wherein each of the plurality of storage units comprises: channel layers distributed in a direction perpendicular to the surface of a substrate; a plurality of interlayer insulation layers and a plurality of gate electrode stacked structures which are laminated alternately along side walls of the channel layers; a plurality of floating gates which are located between the plurality of interlayer insulation layers and the side walls of the channel layers; drain electrodes which are located on the tops of the channel layers; and source electrodes which are located in the substrates between every two adjacent storage units of the plurality of storage units. By means of the three-dimensional semiconductor device and the manufacturing method therefor, floating gates are implanted into side walls of vertical channels, and the opening of source and drain regions generated inductively on the side walls of vertical channels is controlled through the coupling between the gate electrodes and the floating gates, thereby effectively improving the induction efficiency and intensity of the source and drain regions and reducing the source and drain resistance of the storage units, so that the reading current and reading speed of a storage array are increased. |
