Leakage Resistant RRAM/MIM Structure

摘要

An integrated circuit device includes a resistive random access memory (RRAM) cell or a MIM capacitor cell having a dielectric layer, a top conductive layer, and a bottom conductive layer. The dielectric layer includes a peripheral region adjacent an edge of the dielectric layer and a central region surrounded by the peripheral region. The top conductive layer abuts and is above dielectric layer. The bottom conductive layer abuts and is below the dielectric layer in the central region, but does not abut the dielectric layer the peripheral region of the cell. Abutment can be prevented by either an additional dielectric layer between the bottom conductive layer and the dielectric layer that is exclusively in the peripheral region or by cutting of the bottom electrode layer short of the peripheral region. Damage or contamination at the edge of the dielectric layer does not result in leakage currents.

主权项

1. An integrated circuit device, comprising:
a metal-insulator-metal structure including a first dielectric layer between a top conductive layer and a bottom conductive layer; wherein the first dielectric layer comprises:
a peripheral region adjacent an edge of the first dielectric layer where the first dielectric layer has been cut off by etching; anda central region surrounded by the peripheral region; and the top conductive layer abuts and is above the central region of the first dielectric layer; the bottom conductive layer abuts and is below the central region of the first dielectric layer; and wherein the bottom conductive layer does not abut the peripheral region of the first dielectric layer.