发明名称 半導体集積回路およびイメージセンサ
摘要 <p>According to one embodiment, a semiconductor integrated circuit includes: a CDS (Correlated Double Sampling) circuit; and an adjustment voltage generator. The CDS circuit has a first capacitor and a second capacitor. The first capacitor has a first electrode and a second electrode. The second capacitor has a third electrode and a fourth electrode. The CDS circuit is configured to hold a voltage corresponding to light intensity as a signal voltage. The adjustment voltage generator is configured to supply an adjustment voltage to the CDS circuit. A first signal voltage is supplied to the first electrode, and a second signal voltage is supplied to the third electrode. The second electrode and the fourth electrode are commonly connected and supplied with the adjustment voltage from the adjustment voltage generator.</p>
申请公布号 JP5802180(B2) 申请公布日期 2015.10.28
申请号 JP20120198671 申请日期 2012.09.10
申请人 发明人
分类号 H04N5/378;H01L27/146 主分类号 H04N5/378
代理机构 代理人
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