| 摘要 |
An apparatus comprising a decoder circuit, a memory circuit and a processing circuit. The decoder circuit may be configured to generate a first intermediate signal having a plurality of coefficients of a target layer and a plurality of coefficients of a base layer, in response to an input bitstream. The memory circuit may be configured to (i) store the first intermediate signal and (ii) present (a) a second intermediate signal comprising the plurality of coefficients of the target layer or (b) a third intermediate signal comprising the plurality of coefficients of the base layer. The processing circuit may be configured to (i) switch a plurality of times between the coefficients of the target layer and the coefficients of the base layer while reading a frame from the memory circuit, (ii) transform the coefficients of the base layer into base layer information, (iii) buffer the base layer information, where the base layer information buffered at any time comprises at most a subset of macroblock rows of the frame and (iv) generate an output signal comprising a plurality of target layer samples in response to the second intermediate signal and the base layer information as buffered. |
