发明名称 |
Jitter buffer controller |
摘要 |
<p>Provided is a jitter buffer controller for controlling a jitter buffer (2) in which arrived packets are accumulated, including: a jitter measuring portion (8) for measuring jitter in the arrived packets; a judging portion (10) for judging whether or not the jitter of the packets can be absorbed with an accumulation capacity of the jitter buffer (2); a determining portion (6) for determining levels of importance of the packets; and a control portion (4) for reproducing or discarding packets in the jitter buffer (2), having jitter that cannot be absorbed with the accumulation capacity of the buffer, depending on a level of importance of the packets.</p> |
申请公布号 |
EP1838066(B1) |
申请公布日期 |
2015.10.28 |
申请号 |
EP20060253754 |
申请日期 |
2006.07.18 |
申请人 |
FUJITSU LIMITED |
发明人 |
MAKIUCHI, TAKASHI;SUZUKI, MASANAO;OTANI, TAKESHI;TANAKA, MASAKIYO |
分类号 |
H04L29/06;G10L15/28;H04J3/06;H04L12/26 |
主分类号 |
H04L29/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|