High-speed successive approximation analog-to-digital converter

摘要

A successive approximation register analog-to-digital converter (SAR ADC) for high-speed applications. The SAR ADC uses at least one set of capacitors. Each set of capacitors is formed by 2M capacitor cells. The set of 2M capacitor cells is allocated into p capacitors C(p−1) to C0 decreasing in capacitance. C(p−1)

主权项

1. A successive approximation register analog-to-digital converter, comprising:
a successive approximation register subcircuit, generating digital control bits in different cycles of a search scheme of the successive approximation register analog-to-digital converter; a digital-to-analog converter, comprising at least one set of capacitors and coupling an analog input of the successive approximation register analog-to-digital converter to the at least one set of capacitors and operating the at least one set of capacitors in accordance with the digital control bits, wherein each set of capacitors comprises p capacitors Cp-1 to C0 decreasing in capacitance, the p capacitors Cp-1 to C0 are formed by 2M capacitor cells, Cp-1