| 主权项 |
1. A semiconductor integrated circuit comprising a central processing unit, a built-in memory, and a pulse generating circuit,
the pulse generating circuit comprising a rise setting register, a fall setting register, a phase adjustment data register, a cycle data register, a phase arithmetic circuit, a counter, a 1st comparator, a 2nd comparator, and a pulse generator, wherein the counter starts to count up, incrementing its count value from a count initial value, wherein the cycle data register stores, as cycle data, a count maximum value for the counter to count up to it, wherein, when the count value of the counter has reached the count maximum value after the counter starts to count up from the count initial value, the count value of the counter returns to the count initial value again and the counter restarts to count up, wherein the rise setting register stores a rise setting count value of the counter to make a pulse output signal being generated by the pulse generator rise from a low level to a high level, wherein the fall setting register stores a fall setting count value of the counter to make a pulse output signal being generated by the pulse generator fall from the high level to the low level, wherein, in response to detection of a match occurring between the count value of the counter and the rise setting count value, detected by the 1st comparator, the pulse generator makes the pulse output signal change from the low level to the high level, wherein, in response to detection of a match occurring between the count value of the counter and the fall setting count value, detected by the 2nd comparator, the pulse generator makes the pulse output signal change from the high level to the low level, wherein the phase adjustment data register stores a phase angle change value for timing adjustment of the pulse output signal being generated by the pulse generator, wherein the phase arithmetic circuit in the pulse generating circuit comprises a digital multiplying circuit, a digital dividing circuit, a digital adding circuit, and a digital subtracting circuit, wherein the digital multiplying circuit generates a multiplication output signal by performing multiplication of the phase angle change value stored in the phase adjustment data register and the count maximum value stored in the cycle data register, wherein the digital dividing circuit generates a division output signal by dividing the multiplication output signal from the digital multiplying circuit by a phase angle for one cycle, wherein the digital adding circuit is capable of adding the division output signal from the digital dividing circuit and the rise setting count value stored in the rise setting register as well as adding the division output signal and the fall setting count value stored in the fall setting register, wherein the addition performed by the digital adding circuit generates a new rise setting count value and a new fall setting count value required to delay the phase by the phase angle change value, wherein the digital subtracting circuit is capable of subtracting the division output signal from the digital dividing circuit from the rise setting count value stored in the rise setting register as well as subtracting the division output signal from the fall setting count value stored in the fall setting register, and wherein the subtraction performed by the digital subtracting circuit generates a new rise setting count value and a new fall setting count value required to advance the phase by the phase angle change value. |
