发明名称 Timing adjustment circuit and semiconductor integrated circuit device
摘要 A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.
申请公布号 US9172385(B2) 申请公布日期 2015.10.27
申请号 US201414508739 申请日期 2014.10.07
申请人 SOCIONEXT INC. 发明人 Matsuda Atsushi
分类号 H03L7/06;H03L7/085 主分类号 H03L7/06
代理机构 Arent Fox LLP 代理人 Arent Fox LLP
主权项 1. A timing adjustment circuit comprising: a voltage-controlled delay line configured to receive an input clock signal and generate multi-phase clocks, a delay amount of each of the multi-phase clocks being changed according to a control voltage; a phase detector configured to detect a phase difference between a first clock and a second clock, the first clock being a reference, the second clock being generated from the voltage-controlled delay line; a control voltage generation circuit configured to generate the control voltage on the basis of the detected phase difference; and a startup circuit configured to operate for a certain period after activation, and continuously change the control voltage between a first voltage and a second voltage.
地址 Yokohama JP