| 摘要 |
An analog to digital conversion device with DC offset mismatch compensation comprises a composite analog to digital converter (ADC) consisting of N interleaved sub-ADCs, a DC offset accumulator, an averaging unit, a subtraction unit, and a compensation unit. The ADC generates a stream of digital samples corresponding to signal values at an analog input to the ADC. The digital stream is a combination of N partial signals produced by the respective sub-ADCs. The DC offset accumulator measures and stores DC offsets of the respective partial signals. The averaging unit calculates an average value of DC offsets of the respective N partial signals. The subtraction unit is responsive to the DC offsets of the respective partial signals and the average value of the DC offsets, to produce a signal representative of the differences between the values arriving at a DC offset input and the value arriving at an average value input. The subtraction unit is responsive to the DC offsets of the respective partial signals and the average value of the DC offsets, to produce a signal representative of the differences between the values arriving at the DC offset input and the value arriving at the average value input. The compensation unit corrects the digital stream from the ADC by subtracting the differences from the stream from the ADC. |
| 主权项 |
1. An analog to digital conversion device with DC offset mismatch compensation, comprising:
a composite analog to digital converter (ADC) characterized by a system sampling rate S and including N interleaved sub-ADCs,
wherein the ADC includes an analog input common to inputs of the N sub-ADCs, and a composite ADC output,wherein the N sub-ADCs each include a sampling clock input for receiving an associated one of a set of interleaved sequences of sub-ADC sampling clock signals having sub-ADC sampling clock rates S/N,wherein each of the respective sub-ADCs is responsive to its associated sub-ADC sampling clock signal and an analog signal at the input of the ADC, to generate and provide at an associated sub-ADC output, a stream of digital samples of a partial converted digital signal corresponding to portions of an analog signal at the analog input at the sample times of the respective sub-ADC sampling clock signals, and characterized by a DC offset associated with the respective one of the sub-ADCs and otherwise corresponding to instantaneous values of an associated portion of the analog signal,wherein the composite ADC is responsive to the streams of digital samples provided by the respective sub-ADCs, to generate and provide at the output of the ADC, a composite ADC output signal including the partial converted digital signals from the N sub-ADCs, a DC offsets accumulator having an input connected to the output of the ADC and an output, said DC offsets accumulator being adapted to measure and provide at its output, a DC offset of each partial converted digital signal provided at the output of the ADC, an averaging unit having an input connected to the output of the DC offsets accumulator, and an output, wherein the averaging unit is responsive to the measurements provided at the outputs of the DC offsets accumulator, to calculate and provide at an averaging unit output, a value corresponding to an average value of the measured DC offsets of the respective partial converted digital signals; a subtraction unit having a DC offsets input connected to the outputs of the DC offsets accumulator, an average value input connected to the output of the averaging unit, and an output, wherein the subtraction unit generates and provides at its output, corrections signals corresponding to differences between the measured DC offset of each partial converted digital signal provided at the output of the ADC and the average value of the measured DC offsets of the respective partial converted digital signals provided by the averaging unit, and a compensation unit having a signal input connected to the output of the composite ADC, a correction input connected to the output of the subtraction unit, and an output, wherein the compensation unit subtracts the corrections signals at the correction input from the corresponding partial converted digital signals at the signal input, thereby providing at the output of the compensation unit, a sequence of digital samples at the system sampling rate S corresponding to all portions of the analog signal and characterized by substantially no DC offset mismatch for the respective portions of the analog signal. |
