发明名称 | Methods and apparatus for frame detection | ||
摘要 | One embodiment relates to a frame detection circuit for detecting a frame boundary. The circuit includes at least two frame buffers and a staged-parallel structure of syndrome computation circuits that computes a number of syndromes in one cycle. The two frame buffers are each one word in width. The number of syndromes computed in one cycle by the cascaded series is a fraction of a number of bits in one word. Another embodiment relates to a method for detecting a frame boundary. Another embodiment relates to a method for computing a current syndrome. Other embodiments, aspects, and features are also disclosed. | ||
申请公布号 | US9172505(B1) | 申请公布日期 | 2015.10.27 |
申请号 | US201213624095 | 申请日期 | 2012.09.21 |
申请人 | Altera Corporation | 发明人 | Yang Haiyun;Ngo Ninh D. |
分类号 | H04L1/00;H04L25/02 | 主分类号 | H04L1/00 |
代理机构 | Okamoto & Benedicto LLP | 代理人 | Okamoto & Benedicto LLP |
主权项 | 1. A frame detection circuit for detecting a frame boundary in a sequence of bits, the circuit comprising: a first buffer for storing a first received frame of bits, wherein a width of the first buffer is a number of bits in one word in the sequence of bits; a second buffer for storing a second received frame of bits, wherein a width of the second buffer is the number of bits in the one word; and a staged-parallel structure of syndrome computation circuits that computes a number of syndromes in one cycle, wherein the number of the syndromes computed in one cycle is a fraction of the number of bits in the one word, and wherein each syndrome computation circuit in the staged-parallel structure has inputs consisting of a preceding syndrome, a head bit from the first received frame and a tail bit from the second received frame. | ||
地址 | San Jose CA US |