发明名称 Electrostatic discharge protection for three dimensional integrated circuit
摘要 The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, the trigger line controlling the power of a power clamp in each respective die, a dedicated electrostatic discharge (ESD) line for each respective die, and an ESD detection circuit connected to the dedicated ESD line and to a first power line common to the other dies. When an input signal is received by the ESD detection circuit of one of the plural dies, the ESD detection circuit generates an output signal to the common trigger line to supply power to the power clamp in each of the plural dies to clamp ESD voltage or current to the common first power line or a second power line.
申请公布号 US9172242(B2) 申请公布日期 2015.10.27
申请号 US201213667072 申请日期 2012.11.02
申请人 Taiwan Semiconductor Manufacturing Co., Ltd. 发明人 Chang Tzu-Heng;Tseng Jen-Chou;Song Ming-Hsiang
分类号 H02H9/00;H02H9/04 主分类号 H02H9/00
代理机构 Duane Morris LLP 代理人 Duane Morris LLP
主权项 1. An electrostatic discharge (ESD) protection arrangement comprising: a trigger line common to each die in a three dimensional integrated circuit, the three dimensional circuit including a first die disposed over and coupled to at least one second die, the first die being coupled to the at least one second die by at least one through-substrate via; an ESD line specific to each die in the three dimensional integrated circuit; and an ESD detection circuit connected to the ESD line and to a first power line, wherein when an input signal is received by the ESD detection circuit, the ESD detection circuit is configured to provide an output signal to the trigger line to control a power clamp in each die.
地址 Hsin-Chu TW