| 发明名称 |
System and method for virtual hardware memory protection |
| 摘要 |
A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented. |
| 申请公布号 |
US9170956(B2) |
申请公布日期 |
2015.10.27 |
| 申请号 |
US201313896941 |
申请日期 |
2013.05.17 |
| 申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
Chavali Balatripura Sodemma;Greb Karl Friedrich;Suvarna Rajeev |
| 分类号 |
G06F12/00;G06F12/14;G06F13/16 |
主分类号 |
G06F12/00 |
| 代理机构 |
|
代理人 |
Chan Tuenlap D.;Cimino Frank D. |
| 主权项 |
1. A memory protection unit, comprising:
hardware logic to:
receive a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID) indicating a safety level of the transaction, wherein the virtual CPU is implemented on a physical CPU; anddetermine whether to grant or deny access to the bus slave based on the safety level indicated by the virtual CPU ID;wherein the virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented. |
| 地址 |
Dallas TX US |
