发明名称 |
Efficient controllers and implementations for elastic buffers |
摘要 |
Systems and methods relating to an elastic buffer for dynamically adjusting depth of a data-path implemented on an integrated circuit device. The device includes a first flip-flop, a second flip-flop, a multiplexer, and a controller. The first and second flip-flops are arranged in a cascade configuration with the multiplexer interposed therebetween. In certain embodiments, the multiplexer is capable of selecting between input received upstream and the output of the first flip-flop. The controller utilizes control logic to drive the first and second flip-flops and the multiplexer. The first and second flip-flops, and the multiplexer may represent an elastic buffer subunit corresponding to a single bit within a larger elastic buffer, in which a plurality of elastic buffer subunits are cascaded to form the elastic buffer along with a single shared controller. |
申请公布号 |
US9172379(B1) |
申请公布日期 |
2015.10.27 |
申请号 |
US201414497827 |
申请日期 |
2014.09.26 |
申请人 |
Altera Corporation |
发明人 |
How Dana |
分类号 |
G06F7/38;H03K19/173;H03K19/177;G06F17/50 |
主分类号 |
G06F7/38 |
代理机构 |
Ropes & Gray LLP |
代理人 |
Ropes & Gray LLP |
主权项 |
1. An elastic buffer for dynamically adjusting a depth of a data-path implemented on an integrated circuit device, the elastic buffer comprising:
a first flip-flop; a second flip-flop; a multiplexer, wherein the first flip-flop and the second flip-flop are arranged in a cascade configuration with the multiplexer interposed therebetween; and a controller that utilizes control logic to:
drive the first flip-flop and the second flip-flop and the multiplexer, andgenerate enable signals as inputs for each of the first flip-flop and the second flip-flop and a select signal as an input for the multiplexer. |
地址 |
San Jose CA US |