Nonvolatile semiconductor memory device and method of controlling the same

摘要

This nonvolatile semiconductor memory device comprises: a word line connected to a control gate; a bit line electrically connected to one end of a NAND cell unit; a source line electrically connected to the other end of the NAND cell unit; and a control circuit that controls a voltage applied to a semiconductor layer, the control gate, the bit line, and the source line.;The control circuit is configured to, when performing a write verify operation for determining whether a write operation has been completed or not after finishing the write operation, temporarily raise a voltage of the bit line or the source line to a light erase voltage which is higher than a voltage applied to the bit line or the source line during the write verify operation.

主权项

1. A nonvolatile semiconductor memory device, comprising:
a memory cell array having NAND cell units arranged therein, each NAND cell unit configured from a memory string and a select transistor connected to both ends of the memory string, the memory string having a plurality of nonvolatile memory cells connected in series therein, the memory cell including a charge storage layer formed on a semiconductor layer via a gate insulating film and a control gate formed on the charge storage layer via an inter-gate insulating film; a word line connected to the control gate; a bit line electrically connected to one end of the NAND cell unit; a source line electrically connected to the other end of the NAND cell unit; and a control circuit that controls a voltage applied to the semiconductor layer, the control gate, the bit line, and the source line, the control circuit being configured to, when performing a write verify operation for determining whether a write operation has been completed or not after finishing the write operation, temporarily raise, prior to execution of the write verify operation, a voltage of the bit line or the source line to a light erase voltage which is higher than a voltage applied to the bit line or the source line during the write verify operation.