发明名称 |
Providing extended cache replacement state information |
摘要 |
In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed. |
申请公布号 |
US9170955(B2) |
申请公布日期 |
2015.10.27 |
申请号 |
US201213685991 |
申请日期 |
2012.11.27 |
申请人 |
Intel Corporation |
发明人 |
Forsyth Andrew T.;Sundararaman Ramacharan;Sprangle Eric;Mejia John C.;Carmean Douglas M.;Grochowski Edward T.;Cavin Robert D. |
分类号 |
G06F12/08;G06F12/12 |
主分类号 |
G06F12/08 |
代理机构 |
Trop, Pruner & Hu, P.C. |
代理人 |
Trop, Pruner & Hu, P.C. |
主权项 |
1. A processor comprising:
a cache memory including a plurality of entries each to store data and metadata associated with the data, each entry including a first metadata field to store a multi-bit replacement state indicator to indicate one of a plurality of levels of suitability of the data for replacement, wherein multiple ways of a set can be at the same level of the plurality of levels; and control logic coupled to the cache memory to store the replacement state indicator when the data is stored in the entry and to update the replacement state indicator of a first way of a set when second data is to be written into a second way of the set, wherein the control logic is to store a replacement state indicator of a highest level of the plurality of levels responsive to a first user-level instruction that encodes a type of operation and a replacement state indicator of the highest level to indicate that the corresponding data is to be strongly resident, and store a replacement state indicator of a lowest level of the plurality of levels responsive to a second user-level instruction that encodes a type of operation and a replacement state indicator of the lowest level to indicate that the corresponding data is streaming data. |
地址 |
Santa Clara CA US |