Solid state device coding architecture for chipkill and endurance improvement

摘要

A first decoder performs decoding on each data set in a first plurality of data sets using a first code; each data set in the first plurality is stored on a different chip. It is determined if the first decoding is successful; if not, a second decoder performs a second decoding on each data set in a second plurality of data sets using a second code; each data set in the second plurality includes at least some data, after the first decoding using the first code, from each data set in the first plurality. The first decoder performs a third decoding on each data set in the first plurality using the first code, where each data set in the first plurality includes at least some data, after the second decoding using the second code, from each data set in the second plurality.

主权项

1. A system for decoding, comprising:
a first decoder configured to perform a first decoding on a first encoded data set, associated with a first plurality of data sets, using a first error correction code, wherein:
the first encoded data set is obtained from a first semiconductor device;a second data set, associated with the first plurality of data sets, has not yet been received for storage; andthe values of a dummy data set, which substitutes for the not-yet-received second data set, correspond to an erased state; and a second decoder configured to perform a second decoding on each data set in a second plurality of data sets using a second error correction code, wherein:
the first encoded data set and the dummy data set are divided up amongst the second plurality of data sets; andparity information associated with the second error correction code is obtained from a third semiconductor device, wherein a second semiconductor device, which corresponds to the not-yet-received second data set, is not accessed in order to obtain the values of the dummy data set.