发明名称 |
Analog front end for DTV, DTV system having the same, and operation methods thereof |
摘要 |
Provided is an analog front end of a digital TV, a digital TV system having the same, and a method of operating the same. The analog front end includes: a first selection circuit which selectively outputs differential sound intermediate frequency signals or differential TV broadcast signals in response to a first selection signal; a second selection circuit which outputs a clock signal among a plurality of clock signals having a different sampling frequencies, in response to a second selection signal; and an analog-to-digital converter which converts output signals output from the first selection circuit to a digital code, according to a sampling frequency of a clock signal output from the second selection circuit. |
申请公布号 |
US9172988(B2) |
申请公布日期 |
2015.10.27 |
申请号 |
US201414281016 |
申请日期 |
2014.05.19 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
Kim Sang Ho;Park Ho Jin;Koo Hyung Woan;Lee Ki Ho |
分类号 |
H04N5/455;H04N21/426;H04N5/46;H04N5/14;H04N5/50;H04N5/60;H04N21/439 |
主分类号 |
H04N5/455 |
代理机构 |
Sughrue Mion, PLLC |
代理人 |
Sughrue Mion, PLLC |
主权项 |
1. A signal processing circuit comprising:
an analog-to-digital converter which converts differential analog signals to a digital code, in response to a sampling clock signal input to the analog-to-digital converter; a fractional-N phase locked loop (PLL) which receives a clock signal as an input clock signal; and a first selector which receives the clock signal and an output clock signal output from the fractional-N PLL, and which selectively outputs, in response to a first selection signal, one of the received clock signal and the received output clock signal as the sampling clock signal. |
地址 |
Suwon-si KR |