发明名称 Memory system
摘要 A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different physical states; and an access circuit operative to make access to the memory cell via the first line and the second line, wherein the access circuit, on writing data in the access cell, uses a non-access-side first line driver to electrically connect a non-access first line adjacent to an access first line to a first potential power supply via a diode-connected transistor.
申请公布号 US9171598(B2) 申请公布日期 2015.10.27
申请号 US201314079005 申请日期 2013.11.13
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Toda Haruki
分类号 G11C8/00;G11C8/08 主分类号 G11C8/00
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A memory system, comprising: a cell array including a unit cell array, said unit cell array containing plural first lines, plural second lines intersecting said plural first lines, and plural memory cells provided at the intersections of said plural first lines and said plural second lines and operative to store data in accordance with different physical states; and an access circuit operative to make access to said memory cell via said first line and said second line, wherein an access-targeted memory cell of said plural memory cells is defined as an access cell, a first line connected to said access cell of said plural first lines is defined as an access first line and other first lines as non-access first lines, said access circuit includes two first line drivers each operative to alternately control said first lines on alternate lines, one first line driver for controlling said access first line of said two first line drivers is defined as an access-side first line driver and the other first line driver as a non-access-side first line driver, said access-side first line driver and said non-access-side first line driver being arranged across said unit cell array from each other, and said access circuit, on writing data in said access cell, uses said non-access-side first line driver to electrically connect said non-access first line adjacent to said access first line to a first potential power supply via a diode-connected transistor.
地址 Minato-ku JP