Resistive changing memory cell architecture having a select transistor coupled to a resistance changing memory element

摘要

A resistance changing memory array architecture includes an array of resistance changing memory unit cell arranged in rows and column, wherein at least two adjacent columns share a sense bit line, and a control line individually associated with each column, wherein a current control component within each unit cell along a respective column is coupled to a respective control line. The architecture further includes a plurality of word lines each associated with a respective row, wherein a resistance changing element associated with each unit cell along a respective row is coupled to a respective word line.

主权项

1. A resistance changing memory array architecture, comprising:
an array of memory unit cells arranged in rows and columns, wherein at least two of the columns share a first data line, and at least two of the columns share a second data line; a first plurality of signal lines coupled to the columns of memory unit cells, wherein a current control component within each memory unit cell along a respective column is coupled to a respective signal line of the first plurality of signal lines; a second plurality of signal lines coupled to the rows of memory unit cells, wherein a resistance changing element associated with each memory unit cell along a respective row is coupled to a respective signal line of the second plurality of signa lines; and a control circuit configured to:
provide different control signals along the signal lines of the first plurality of signal lines coupled to the at least two columns that share the first data line, andprovide a sequence of control signals along the second data line in a sequence dictated by a programming sequence of resistance changing elements in memory unit cells along the at least two columns that share the second data line.