Array substrate, method for controlling the same and display panel including the array substrate

摘要

According to an embodiment of the invention, there is disclosed an array substrate, comprising: data lines; first and second gate lines, the first and second gate lines and the data lines crossing with each other so as to define sub-pixel structures; each of the sub-pixel structures comprising first and second sub-pixels; a first control line, insulated from the first and second gate lines; and first switch devices, each for making the first gate line and the second gate line corresponding to the first sub-pixel and the second sub-pixel in the same sub-pixel structure connected or disconnected under the control of the first control line, wherein in each of the sub-pixel structures, the first gate line is connected to the first sub-pixel, the second gate line is connected to the second sub-pixel, and the first sub-pixel and the second sub-pixel are connected to the same data line.

主权项

1. An array substrate, comprising:
data lines; first gate lines and second gate lines, the first and second gate lines and the data lines crossing with each other so as to define a plurality of sub-pixel structures arranged in a matrix form; each of the plurality of sub-pixel structures comprising a first sub-pixel and a second sub-pixel, and each of the first sub-pixel and the second sub-pixel including a pixel electrode and a thin film transistor, the thin film transistor for each of them comprising a gate, a source, a drain and an active layer; a first control line, insulated from the first gate lines and the second gate lines; and first switch devices, each for making the first gate line and the second gate line corresponding to the first sub-pixel and the second sub-pixel in the same sub-pixel structure connected or disconnected under the control of the first control line; and a second control line, a third control line and second switch devices each of the second switch devices for making the second control line and the second gate lines connected or disconnected under the control of the third control line, wherein in each of the stab-pixel structures, the first gate line is connected to the first sub-pixel, the second gate line is connected to the second sub-pixel, and the first sub-pixel and the second sub-pixel are connected to the same data line.