Shut-off circuits for latched active ESD FET

摘要

An integrated circuit may include an over-capability detection circuit coupled to an I/O pad which provides a shut-off signal to a latch controlling an ESD protection shunting component. The ESD protection shunting component is coupled between the I/O pad and a reference node of the integrated circuit. The over-capability detection circuit provides the shut-off signal when safe operating conditions are resumed after a voltage excursion at the I/O pad. After receiving the shut-off signal, the latch biases the ESD protection shunting component into an off-state.

主权项

1. An integrated circuit, comprising:
a functional circuitry; an input/output (I/O) pad coupled to functional circuitry; an electrostatic discharge (ESD) protection shunting component coupled between the I/O pad and a reference node of the integrated circuit; a latch configured to turn on the ESD protection shunting component in response to an ESD signal and to turn off the ESD protection shunting component in response to a shut-off signal; an ESD detection circuit coupled with said I/O pad, the ESD detection circuit configured to provide the ESD signal to the latch which causes said latch to turn on the ESD protection shunting component; and an over-capability detection circuit including a current sensor coupled in series with the ESD protection shunting component, the over-capability detection circuit configured to provide the shut-off signal to the latch which causes said latch to turn off the ESD protection shunting component.