发明名称 |
CACHE MEMORY ERROR DETECTION CIRCUITS FOR DETECTING BIT FLIPS IN VALID INDICATORS IN CACHE MEMORY FOLLOWING INVALIDATE OPERATIONS, AND RELATED METHODS AND PROCESSOR-BASED SYSTEMS |
摘要 |
Aspects disclosed herein include cache memory error detection circuits for detecting bit flips in valid indicators (e.g., valid bits) in cache memory following invalidate operations. Related methods and processor-based systems are also disclosed. If a cache hit results from access to a cache entry following an invalidate operation, a bit flip(s) has occurred in a valid indicator of the cache entry. This is because the valid indicator should indicate an invalid state following the invalidate operation of the cache entry, as opposed to a valid state. Thus, a cache memory error detection circuit is configured to determine if an invalidate operation was performed on the cache entry. The cache memory error detection circuit can cause a cache miss or an error for the accessed cache entry to be generated as a result, even though the valid indicator for the cache entry indicates a valid state due to the bit flip(s). |
申请公布号 |
WO2015160493(A1) |
申请公布日期 |
2015.10.22 |
申请号 |
WO2015US23269 |
申请日期 |
2015.03.30 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
INGALLS, JOHN, SUMNER;STEMPEL, BRIAN, MICHAEL;SPEIER, THOMAS, PHILIP |
分类号 |
G06F11/10;G06F12/08 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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