发明名称 TERMINAL ARRANGEMENT DEVICE AND TERMINAL ARRANGEMENT METHOD
摘要 <p>PROBLEM TO BE SOLVED: To provide a terminal arrangement device and a terminal arrangement method that are able to accurately estimate simultaneous operation output noise, taking account of increase in the parasitic capacitance due to a non-connection pad.SOLUTION: A terminal arrangement device comprises: an instruction acquiring section; a terminal arrangement information editing section that edits correlation between a semiconductor chip pad and a package pin so that an instructed number of non-connection pads are arranged in instructed positions; a simultaneous operation output check section configured such that, taking account of increase in the parasitic capacitance due to the arrangement of the number of non-connection pads arranged, when two or more output buffer cells corresponding to output pads between the first and second power source pads operate simultaneously, it is checked whether or not the total drive coefficient corresponding to the total drive capability of output buffer cells simultaneously operated satisfies a permissible drive coefficient corresponding to the drive capability of the first power source; and a check result output section configured to output a check result.</p>
申请公布号 JP2015184860(A) 申请公布日期 2015.10.22
申请号 JP20140059731 申请日期 2014.03.24
申请人 MEGA CHIPS CORP 发明人 KIRYU HIROYOSHI
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04 主分类号 G06F17/50
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