GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS

摘要

A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

主权项

1. A non-volatile memory device, comprising:
a plurality of wordlines (WLs); a plurality of local bitlines (LBLs) selectively electrically coupled with a plurality of global bit lines (GBLs); a plurality of re-writable non-volatile two-terminal memory elements, each memory element positioned between a cross-point of one of the plurality of WLs with one of the plurality of LBLs and each memory element directly electrically in series with its respective WL and LBL; and a plurality of amplifiers electrically coupled with the plurality of LBLs and the plurality of GBLs.