CONNECTION STRUCTURE FOR VERTICAL GATE ALL AROUND (VGAA) DEVICES ON SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE

摘要

A vertical gate all around (VGAA) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of VGAA nanowire devices including a NMOS and a PMOS device. The devices are formed on a semiconductor-on-insulator substrate. Each device comprises a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other serves as a source node. Each device further comprises a gate layer. The gate layer fully surrounds a vertical channel in the device. In one example, a CMOS circuit is formed with an oxide (OD) block layer that serves as a common bottom plate for the NMOS and PMOS devices. In another example, a CMOS circuit is formed with a top plate that serves as a common top plate for the NMOS device and the PMOS devices. In another example, a SRAM circuit is formed.

主权项

1. A vertical gate all around (VGAA) nanowire device circuit routing structure, the circuit routing structure comprising:
a plurality of VGAA nanowire devices including a NMOS VGAA nanowire device and a PMOS VGAA nanowire device, the VGAA nanowire devices being formed on a semiconductor-on-insulator (SOI) substrate, each of the VGAA nanowire devices comprising a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other of the bottom and top plates serves as a source node, each of the VGAA nanowire devices further comprising a gate layer, the gate layer comprising a high-K gate dielectric and a metal layer, the gate layer fully surrounding a vertical channel in the VGAA nanowire device and serving as a gate node; and a CMOS circuit formed by the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the CMOS circuit comprising an oxide diffusion (OD) block layer that serves as a common bottom plate for the NMOS VGAA nanowire device and the PMOS VGAA nanowire device to electrically connect the drain node of the NMOS VGAA nanowire device to the drain node of the PMOS VGAA nanowire device, the CMOS circuit further comprising a first gate layer that serves as a common gate for the NMOS VGAA nanowire device and the PMOS VGAA nanowire device to electrically connect the gate node of the NMOS VGAA nanowire device to the gate node of the PMOS VGAA nanowire device, the CMOS circuit further comprising a first top plate that serves as the source node for the NMOS VGAA nanowire device and a second top plate that serves as the source node for the PMOS VGAA nanowire device, wherein the first top plate is electrically connected to a Vss conductor and the second top plate is electrically connected to a Vdd conductor.