| 发明名称 |
BACK END OF LINE (BEOL) LOCAL OPTIMIZATION TO IMPROVE PRODUCT PERFORMANCE |
| 摘要 |
The disclosure relates to a locally optimized integrated circuit (IC) including a first portion employing one or more metal interconnects having a first metal width and/or one or more vias having a first via width, and a second portion employing one or more metal interconnects having a second metal width and/or one or more vias having a second via width, wherein the second portion comprises a critical area of the IC, and wherein the second metal width is greater than the first metal width and the second via width is greater than the first via width. A method of locally optimizing an IC includes forming the one or more metal interconnects and/or the one or more vias in the first portion of the IC, and forming the one or more metal interconnects and/or the one or the more vias in the second portion of the integrated circuit. |
| 申请公布号 |
US2015303145(A1) |
申请公布日期 |
2015.10.22 |
| 申请号 |
US201414255820 |
申请日期 |
2014.04.17 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
ZHU John Jianhong;CHIDAMBARAM PR;NALLAPATI Giridhar;YEAP Choh Fei |
| 分类号 |
H01L23/528;H01L21/768;G06F1/18 |
主分类号 |
H01L23/528 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A locally optimized integrated circuit, comprising:
a first portion employing one or more metal interconnects having a first metal width and/or one or more vias having a first via width; and a second portion employing one or more metal interconnects having a second metal width and/or one or more vias having a second via width, wherein the second portion comprises a critical area of the integrated circuit, and wherein the second metal width is greater than the first metal width and the second via width is greater than the first via width. |
| 地址 |
San Diego CA US |
