发明名称 NONVOLATILE MEMORY DEVICES HAVING CHARGE TRAPPING LAYERS AND METHODS OF FABRICATING THE SAME
摘要 A nonvolatile memory device includes a substrate having a first charge trap region, a second charge trap region, and a selection region between the first and second charge trap regions. A well region is disposed in the substrate. A source region and a drain region are disposed in the well region. A gate structure is disposed on a channel region between the source region and the drain region. The gate structure includes: a first tunneling layer, a first charge trap layer, a first blocking layer and a first conductive layer stacked in the first charge trap region; a second tunneling layer, a second charge trap layer, a second blocking layer and a second conductive layer stacked in the second charge trap region; and a first insulation layer, a second insulation layer, a third insulation layer and a third conductive layer stacked in the selection region.
申请公布号 US2015303204(A1) 申请公布日期 2015.10.22
申请号 US201414341567 申请日期 2014.07.25
申请人 SK hynix Inc. 发明人 KWON Young Joon
分类号 H01L27/115;H01L21/28;H01L29/66;H01L29/10;H01L29/51;H01L29/792 主分类号 H01L27/115
代理机构 代理人
主权项 1. A nonvolatile memory device comprising: a substrate having a first charge trap region, a second charge trap region, and a selection region between the first and second charge trap regions, wherein the first charge trap region, the selection region and the second charge trap region are arrayed in one direction; a well region having a first conductivity type and disposed in the substrate, wherein a surface of the well region is exposed; a source region and a drain region disposed in the well region to be separated from each other by a channel region, wherein the source region and the drain region have a second conductivity type different from the first conductivity type; and a gate structure disposed on the channel region, wherein the gate structure includes: a first tunneling layer, a first charge trap layer, a first blocking layer and a first conductive layer, stacked in the first charge trap region; a second tunneling layer, a second charge trap layer, a second blocking layer and a second conductive layer stacked in the second charge trap region; and a first insulation layer, a second insulation layer, a third insulation layer and a third conductive layer stacked in the selection region.
地址 Gyeonggi-do KR