Through-Polymer Via (TPV) and Method to Manufacture Such a Via

摘要

Vias for three dimensional (3D) stacking, packaging and heterogeneous integration of semi-conductor layers and wafers and a process for the manufacture of a via, to a via, to a 3D circuit and to a semiconductor device. Vias are interconnects used to vertically interconnect chips, devices, interconnection layers and wafers, i.e., in an out-of-plane direction.

主权项

1. A process for the manufacture of a via for three dimensional stacking, packaging and/or heterogeneous integration of semiconductor devices and/or wafers comprising:
(a) providing a microstructure of polymer on a carrier layer or substrate; (b) coating the microstructure with a layer of a first electrically conducting material to provide a coated microstructure; and (c) encapsulating the coated microstructure within a second electrically insulating material such that the coated microstructure forms an interconnect between upper and lower surfaces of the second electrically insulating material.